Develop RTL designs using Verilog/SystemVerilog based on architecture specifications.
Define and implement digital micro-architecture for SoC/IP blocks.
Design and integrate modules related to:
Motor Control Systems
Industrial Communication Interfaces
Embedded Controllers
DMA, Interrupt Controllers
GPIO, Timers, PWM Modules
UART, SPI, I2C, CAN, Ethernet Interfaces
Perform RTL coding, linting, CDC and quality checks.
Analyze architecture specifications and convert them into RTL implementation.
Support functional verification teams during simulation and debug activities.
Collaborate with DFT teams for scan insertion and testability requirements.
Work with Synthesis and Physical Design teams to close implementation issues.
Participate in RTL reviews, design reviews, and code reviews.
Prepare RTL documentation and design specifications.

Roles and Responsibilities




A seasoned technical leader with deep expertise in semiconductor design and development, the Senior Principal Engineer plays a pivotal role in driving innovation across all phases of chip development — from architecture and RTL design to physical implementation, verification, and silicon validation. This role is responsible for setting technical direction on cutting-edge projects, influencing product roadmaps, and ensuring the successful delivery of high-performance, low-power, and cost-effective integrated circuits. Acting as a mentor and technical advisor, the Senior Principal Engineer collaborates with cross-functional teams across architecture, design, verification, DFT, and packaging to push the boundaries of silicon technology while aligning engineering execution with business and product strategies.

📌 Rtl Design Engineer Bengaluru
🏢 Cyient
📍 Bengaluru