Job Description

The STA Engineer is responsible for ensuring robust timing closure and signoff readiness for block- and full-chip designs across all modes and corners. This role owns timing constraint development and validation, performs detailed setup/hold and variation-aware analysis, and partners closely with Synthesis, CTS, Physical Design, and Design teams to debug violations and drive ECO-based optimizations through tapeout.

Responsibilities:

- Perform full-chip and block-level Static Timing Analysis (STA) across all modes and corners.
- Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations.
- Work closely with Physical Design, Synthesis, CTS, and Design teams to achieve timing closure.
- Develop and maintain timing constraints including SDC creation, validation, and signoff readiness.
- Drive timing closure through ECO implementation and timing optimization.
- Analyze timing impact due to process, voltage, and temperature variations.
- Support timing signoff for pre-layout and post-layout stages.
- Perform cross-functional reviews for timing convergence and provide recommendations.
- Generate timing reports and communicate closure status to project stakeholders.

📌 Staff Engineer, STA and Synthesis (Bengaluru)
🏢 renesas electronics
📍 Bengaluru