11 Sep
|
LT-Larsen & Toubro
|
Bengaluru
11 Sep
LT-Larsen & Toubro
Bengaluru
Role Summary
Execute and own FPGA prototyping and emulation activities for complex SoC designs, with primary focus on multi-FPGA prototyping, synthesis/P&R;, timing closure, bitfile generation, board bring-up and system-level debug. Support emulator model bring-up on ZeBu/Veloce and collaborate with Design, DV, Firmware and Board teams to resolve issues. Drive assigned technical workstreams, automation and productivity improvements while providing hands-on technical guidance to junior engineers.
Roles & Responsibilities
- Execute end-to-end FPGA prototyping and emulation activities for SoC/ASIC designs, covering RTL preparation, synthesis, partitioning, P&R;, bitfile generation, board bring-up and validation.
- Take ownership of FPGA prototype model bring-up on platforms such as HAPS, Protium and other FPGA-based prototyping systems.
- Support multi-FPGA partitioning and implementation, including partition optimization, FPGA resource utilization, inter-FPGA connectivity, pin utilization and routing challenges.
- Perform FPGA synthesis, P&R; and timing analysis,
identify implementation bottlenecks and work on resolving timing violations, congestion and resource issues.
- Support clock and reset implementation for FPGA prototypes, including analysis of ASIC clock structures and development/application of appropriate FPGA constraints.
- Drive FPGA board bring-up and debug, including JTAG, clocks, resets, memories and SoC interfaces such as SPI, I2C, UART, MDIO, PCIe and other relevant interfaces.
- Develop, generate and validate FPGA bitfiles and support deployment on prototype hardware.
- Perform emulator model bring-up and validation on platforms such as ZeBu and Veloce, including compilation, model configuration, basic connectivity validation and debug.
- Support FPGA prototype and emulator debug using waveform/debug tools, FPGA probes, logs and hardware/software correlation.
- Analyze RTL and implementation reports to identify synthesis, P&R;, timing and emulation-rel
📌 Senior Engineer (Bengaluru)
🏢 LT-Larsen & Toubro
📍 Bengaluru