Hiring: Application Specific Integrated Circuit Design Engineer (Secunderabad)

Hiring: Application Specific Integrated Circuit Design Engineer (Secunderabad)

11 Sep
|
Macrohire
|
Secunderabad

11 Sep

Macrohire

Secunderabad

Job DescriptionASIC Frontend Design Engineer-
NWork Location- Kolkata (3days WFO)
NExp- 1) Engineer (6-12 years & IC role),
N2) Manager (14-20 years)
NMode of Interview- 2 Rounds Virtual followed by last F2F at Bangalore or Kolkata office.
NJD
n-Opportunity Snapsho
NtWe are looking for a highly skilled ASIC Frontend Design Engineer to join our high-performance VLSI team. You will be responsible for designing and delivering next-generation, high-speed ASICs for complex networking and compute systems, while collaborating with global Architecture, Design, Verification, and Physical Design teams. We foster a culture of innovation, ownership, collaboration, and continuous learning, offering excellent opportunities for technical growth and leadership
N.
n Key Responsibiliti
N
- n
- esDesign and develop high-performance ASICs and SoC blocks for next-generation product N
- s.Define microarchitecture, perform RTL design, and optimize for performance, power, and area (PPA N
- ).Develop high-quality RTL using Verilog/SystemVerilo N




- g.Collaborate with Verification teams on test planning, functional coverage, debug, and verification closur N
- e.Work with Physical Design teams on timing constraints, timing analysis, and timing closur N
- e.Participate in designreviews, root-cause analysis, and silicon bring-up activitie N
- s.Drive cross-functional collaboration with Architecture, Verification, Firmware, Physical Design, and Program Management team N

ns.Required Skil
N
- n
- lsStrong RTL coding expertise in Verilog/SystemVerilo N
- g.Valuable understanding ofSoC architecture, microarchitecture, digital logic, and ASIC desig N
- n.Hands-on experience with SystemVerilog, UVM, SVA, coverage-driven verification, and RTL concept N
- s.Knowledge of high-speed protocols such as PCIe, Ethernet, AXI, NoC, DDR/HBM, CXL, UCIe, or cache coherency protocol N
- s.Experience with high-performance memory subsystems, clock-domain crossing (CDC), and high-speed se

📌 Hiring: Application Specific Integrated Circuit Design Engineer (Secunderabad)
🏢 Macrohire
📍 Secunderabad

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