Job DescriptionSOC RTL Design Verification
nExperience: 4 to 10 Years
nLocation: Bangalore
nKey Responsibilities:
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- Verification of SOC RTL (This is a DV Req) : FW-HW co-verification at SOC level, good understanding of SOC boot flow, integration level verificationn
- Development and verification of post-si validation sequences using C/C++n
- Create methodology-based (UVM) verification testbenches and components from scratch at SOC level along with re-usability of IP level components.n
- Experienced with Verilog, System Verilog, and C or C++n
- Positive understanding of JTAG protocoln
- Contributes to test plan development.n

nCandidate past experience requirements,
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- Should have experience in system-level Verification.n




- DDR prior experience is not mandatory.n

nAbout Company:
nACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.
nwww.acldigital.com

📌 RTL Design Verification Engineer (Vasanthanagar)
🏢 ACL Digital
📍 Vasanthanagar