Job DescriptionHiring: Staff Engineer - STA
nLocation: Hyderabad / Bangalore
nExperience: 10+ Years
nNotice Period: Immediate to 30 Days Preferred
nRole Overview
nWe are looking for an experienced Static Timing Analysis (STA) Engineer with strong expertise in timing sign-off for complex SoC designs. The candidate should have hands-on experience in timing closure, constraints development, and working closely with PD and RTL teams to achieve design closure.
nKey Responsibilities
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- Perform block and full-chip Static Timing Analysis for complex SoC designsn
- Develop and validate timing constraints (SDC)n
- Drive timing closure across different corners and modesn
- Analyze and debug setup/hold violationsn
- Work closely with Physical Design, RTL, and Architecture teamsn
- Support ECO implementation for timing fixesn
- Handle timing sign-off for tape-outn
- Perform clock tree and timing path analysisn

nMandatory Skills
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- Strong expertise in Static Timing Analysis (STA)n
- Hands-on experience with Synopsys PrimeTimen
- Strong understanding of timing constraints (SDC)n
- Experience in timing closure and sign-offn
- Understanding of clocking architecture and CDC conceptsn
- Exposure to advanced technology nodesn
- Positive understanding of Physical Design flown

nGood to Have
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- Experience with CPU/GPU or high-performance SoC designsn
- Knowledge of Low Power (UPF/CPF)n
- Exposure to Synthesis and PD flown
- Experience in ECO and sign-off flowsn

nRequired Experience
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- 10+ years of experience in STA / Timing Analysisn
- Strong debugging and problem-solving skillsn
- Ability to work independently and drive timing closuren

nInterested candidates can share resumes with

📌 Staff Engineer (Vasanthanagar)
🏢 BITSILICA
📍 Vasanthanagar