Key Responsibilities:
- Perform physical verification at the SoC, core, and block levels, including DRC, LVS, ERC, ESD, DFM, and tapeout tasks.
- Address complex physical design challenges related to sign-off and ensure timely resolution.
- Maintain deep understanding of physical verification workflows and methodologies across RTL to GDS2.
- Collaborate with Place-and-Route (PNR) teams to support verification sign-offs at various stages.
- Troubleshoot and resolve LVS issues, particularly for complex analog-mixed signal IP integrations.
- Support verification of full-chip components including I/O rings, corner cells, seal rings, RDL routing, and bumps.
- Contribute to the development of sign-off methodologies and provide technical guidance to broader teams.
- Apply knowledge of ERC, PERC, and ESD rule checks to improve design quality.
- Engage in floor planning tasks as needed (preferred but not mandatory).
- Ensure compliance with low-power design practices involving isolation cells, level shifters, power domains, and substrate isolation.