Key Responsibilities
- Implement modular UVM testbenches at the MCU level for SoC subsystems such as sensor hubs, AI accelerators, and communication fabrics
- Develop comprehensive coverage-driven verification plans covering functional, code, and assertion coverage aligned with automotive safety and security standards
- Debug complex SoC-level scenarios including multi-protocol interactions and power-aware verification
- Integrate and customize third-party Verification IPs (VIPs) like Synopsys, Cadence, and Mentor for automotive protocols
- Provide technical leadership and ownership of design verification tasks
- Communicate clearly and transparently within the team and with global customers
- Adapt to agile project requirements and changing timelines
- Contribute creative ideas to improve design quality and verification workflows
📌 Staff Engineer- DV (Secunderabad)
🏢 Renesas
📍 Secunderabad
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