Key Responsibilities
- Lead block-level PNR from floorplanning through routing, ensuring implementation meets timing, power, and area targets
- Design robust power grids and implement EM/IR-aware routing for block-level power integrity
- Work closely with timing engineers to resolve PPA bottlenecks affecting timing and signal integrity
- Manage and optimize physical verification including DRC, LVS, antenna checks, and physical signoff
- Automate PNR flows using scripting to enhance productivity and design quality
- Mentor junior engineers and promote best practices in physical design methodology
- Coordinate with RTL, STA, verification, and backend integration teams for block-to-chip integration