Job DescriptionSenior Analog Layout Engineer
nLocation: Hyderabad, Bangalore
nExperience: 4 to 6 Years
nNotice Period: Immediate
nJob Description:
nKey Responsibilities
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- Custom Layout Design: Lead the layout development of critical analog blocks, including high-speed ADCs/DACs, PLLs, SerDes, Bandgaps, and LDOs.n
- Advanced Node Implementation: Navigate challenges unique to sub-3nm nodes, such as multi-patterning, EUV constraints, and FinFET/GAAFET-specific layout-dependent effects (LDE).n
- Physical Verification: Execute and debug comprehensive verification flows, including DRC, LVS, ERC, Antenna, and Latch-up checks using industry-standard tools.n
- Extraction & Analysis: Perform parasitic extraction (PEX) and collaborate with designers on post-layout simulations to meet stringent timing and performance targets.n
- Floorplanning: Optimize block-level and top-level floorplans to manage IR drop, Electromigration (EM), and Thermal-aware placement.n
- Reliability & DFM: Implement Design for Manufacturability (DFM)



guidelines and ensure robust ESD/latch-up protection strategies.n

nTechnical Skills & Qualifications
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- Education: B.E./B.Tech or M.E./M.Tech in Electronics, VLSI, or Electrical Engineering.n
- EDA Tools: Expert proficiency in Cadence Virtuoso (VXL/GXL) and Mentor Graphics Calibre (DRC/LVS/PEX).n
- Process Experience: Proven track record with FinFET technologies (7nm, 5nm) and direct exposure to 3nm or below nodes.n
- Analog Fundamentals: Deep understanding of matching techniques (Common Centroid, Interdigitation), shielding, and isolation (Deep N-Well, Guard Rings).n
- Scripting (Preferred): Familiarity with SKILL, Perl, or Tcl for layout automation and productivity enhancement.n

nSoft Skills
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- Robust problem-solving skills for debugging complex verification errors.n
- Ability to mentor junior engineers and lead small-scale block integrations.n
- Excellent communication skills for collaborating with global cross-

📌 Analog Layout (Hyderabad)
🏢 ACL Digital
📍 Hyderabad