Responsibilities:
- Lead RTL synthesis and constraints generation/validation for MCU SoCs to meet performance, power, and area targets
- Develop and implement cutting-edge methodologies and tools to improve design quality and engineering productivity
- Act as the key interface between frontend and backend design teams, resolving hand-off and timing-related issues
- Conduct detailed design reviews and provide feedback to peers and junior engineers
- Collaborate with cross-functional teams to resolve design collateral issues and enhance overall PPA (Power, Performance, Area)
- Support low power implementation flows and techniques
- Perform formality checks to ensure RTL vs. netlist equivalence