Location: Bangalore, India
Experience: 3–15 Years
Salary Range: ₹15–50 LPA
Work Mode: Work from office(380)
Notice Period: Immediate to 60 Days
Role Overview
We are looking for experienced DFT Engineers at Senior/Manager level to work on semiconductor/SoC design projects. The ideal candidate should have a strong understanding of DFT concepts and hands-on experience in one or more areas including BSCAN, MBIST, Scan, ATPG, DFT insertion, pattern generation, and simulation.
The role involves working closely with DFT, RTL, STA, Physical Design, verification, and customer-facing teams. Strong technical debugging, communication, and team mentoring skills are essential.
Must-Have Skills
- Strong understanding of DFT fundamentals and concepts including:
- Scan
- ATPG
- MBIST
- BSCAN
- DFT simulation
- Hands-on experience in at least one of the following:
- MBIST insertion
- Scan insertion
- ATPG pattern generation
- ATPG pattern simulation
- MBIST/BSCAN simulation
- Experience with industry-standard DFT tools from Cadence, Siemens Tessent,
or Synopsys.
- Positive understanding of fault models such as:
- Stuck-at
- Transition Delay Fault (TDF)
- IDDQ
- Experience with test coverage analysis and coverage improvement techniques.
- Good debugging skills using GUI-based industry-standard simulators such as VCS, NCSim, or Xcelium.
- Experience working at SoC-level DFT.
- Good understanding/experience of DFT implementation concepts such as:
- OCC / OPCG insertion
- EDT / Compression logic
- Clock handling for scan/test modes
- Ability to debug DFT issues and analyze simulation/pattern failures.
- Experience providing test-mode timing constraints to STA and Physical Design teams.
- Strong communication and collaboration skills for working with cross-functional and customer teams.
Nice-to-Have Skills
- Experience with both Zero-Delay and SDF timing simulations.
- Experience with post-silicon bring-up and/or production activities.
- Exposure to tester