Role Overview

We are seeking an executive technical leader to head our Design Verification (DV) engineering organization. Managing a team of 100+ DV engineers, you will establish verification strategy, UVM testbench architectures, formal verification, and emulation flows across complex IP, Subsystem, and SOC projects.

This role balances large-scale team management and external customer engagement with direct hands-on technical involvement in debugging complex coverage gaps, testbench architectures, and hardware-software co-verification challenges.

Key Responsibilities

1. Team & Resource Management (100+ Engineers)

- Lead, structure, and scale a 100+ engineer Design Verification unit, including Directors, Engineering Managers, and Principal DV Architects.
- Oversee resource deployment, project staffing, code review rigor, and talent retention across SystemVerilog/UVM, Formal, and Emulation tracks.

2. Hands-On Technical Authority & Execution

- Serve as the technical authority for UVM testbench architecture, constrained-random verification, assertion-based verification (SVA), coverage closure, and functional bug tracking.
- Maintain direct technical involvement in setting up formal verification strategies, HW/SW co-verification, and high-speed emulation environments (e.g., Palladium, Zebu,



Veloce).
- Implement CI/CD regressions, coverage-driven automation, and Portable Stimulus Standard (PSS) methodologies to ensure zero-defect silicon.

3. Client Handling & Account Management

- Serve as the senior technical executive interfacing with client VP/Director level stakeholders to present verification metrics, bug-trend curves, and sign-off readiness.
- Partner with customers to define verification plans (vPlans), accept high-complexity IP/SOC deliverables, and resolve program execution blockages.

Required Qualifications

- Education: B.Tech / M.Tech / M.S. in Electrical Engineering, Computer Engineering, or VLSI.
- Experience: 18+ years in ASIC/SOC verification, with at least 4+ years leading Design Verification organizations of 80100+ engineers.
- Domain Mastery: Deep, hands-on mastery of SystemVerilog, UVM, C/C++ drivers, Formal Verification, and Emulation platforms.
- Bug-Free Silicon Track Record: Proven history of leading DV for complex SOCs resulting in first-pass silicon success.
- Client Leadership: Solid experience handling external accounts, managing verification deliverables under strict client SLAs, and leading technical QBRs.

📌 Engineering (Bengaluru)
🏢 ACL Digital
📍 Bengaluru