Designation: Director-FPGA RTL Design /n Bangalore /n : /n Ø As a director will be working on our existing and next generation Protocol Analysers and exercisers and similar products. /n Ø Manages the FPGA design team /n Ø Develop a new products to meet needs top semiconductor for their pre and post silicon validation /n Ø The role involves contributing to the entire FPGA based product development flow starting from requirement analysis till final product testing in lab setting. /n Ø The candidate will be responsible for architecture/micro-architecture design and implementation of the logic in Verilog for targeted FPGA, writing test benches to validate the design etc. /n Ø Job involves working with team of FPGA Design Engineers and deliver the products as planned /n Ø Guides the team to Debugging of designs to resolve complex design issues. /n Ø Job involves frequent interaction with board design, software, testing and lab teams to deliver the product meeting the customer requirements. /n Ø Job involves understanding and working with interfaces such as PCIe, GigE, MPHY/UFS, DPHY/CSI/DSI, USB, SD, eMMC, I3C/I2C, SPI/QSPI etc. /n Ø Contributing to/participating in internal design reviews to ensure adherence to the company FPGA design process.



/n Ø Maintaining all design documents and code base in Github /n Ø Participate and Contribute to the standard bodies such as PCIeSig, MIPI Alliance, SD Association and USB Org /n Ø Owns responsibility filing patents. /n Ø International travel is involved /n Qualifications: /n BE/ME in Electronics from a reputed college. Specialization in VLSI and Embedded Design is a plus. /n Ø 16 to 18 years of experience in designing and implementing FPGA based solution in Xilinx or Altera FPGA, preferably FPGA based product development experience. /n Ø FPGA Based High speed IP development such as PCIe 5.0/6.0, USB4 or DP2.0 /n Ø Has expertise in verification of RTL code /n Ø Must have experience in System Design with Xilinx/Altera FPGA devices with relevant tools. /n Ø Deep expertise in FPGA based data plane design to manage the high-speed serial bus data /n Ø Must have experience in Verilog and/or VHDL coding. /n Ø Must have very good understanding of physical layer of SERDES of XILINX-AMD or Intel FPGA /n Location: Bengaluru, India /n Skills: /n Xilinx /n Altera /n PCIe /n USB /n DP /n Verilog /n VHDL /n Serdes /n GiGE /n UFS /n CSI /n DSI /n MIPI /n Contact: /n Uday /n Mulya Technologies /n [email protected] /n "Mining The Knowledge Community"

📌 Director-FPGA RTL Design (Bengaluru)
🏢 Mulya Technologies
📍 Bengaluru