Location: Bangalore / Hyderabad, India /n Experience: 4–10 Years /n Employment Type: Full-Time /n Role Summary /n We are looking for an experienced Analog Layout Engineer to join our semiconductor design team and work on high-performance analog and mixed-signal IPs in advanced CMOS/FinFET technology nodes. /n The ideal candidate should have robust hands-on experience in full-custom analog layout, preferably with TSMC technology nodes, and a solid understanding of matching, parasitics, advanced layout techniques, and physical verification. /n The role involves working closely with analog circuit designers, physical verification, and other cross-functional teams to deliver high-quality, silicon-ready layouts. /n Key Responsibilities /n /n

- Develop full-custom analog and mixed-signal layouts for complex IC designs.

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- Work on layout of analog building blocks such as:

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- Op-Amps

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- Bandgap references

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- LDOs / Regulators

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- ADC/DAC blocks

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- PLL/DLL

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- Charge Pumps

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- Current/Voltage References

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- High-speed I/O and SerDes/DDR PHY circuits

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- Implement advanced layout techniques including:

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- Common-centroid

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- Interdigitation

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- Symmetry

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- Matching

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- Dummy devices

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- Guard rings

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- Shielding

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- Sensitive-node isolation

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- Perform parasitic-aware layout optimization and minimize the impact of routing and device parasitics on circuit performance.

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- Work closely with analog designers to understand circuit requirements and translate schematics into optimized physical layouts.

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- Perform DRC, LVS,



ERC and other physical verification checks and debug layout issues.

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- Support PEX/post-layout simulation and optimize layouts based on extracted parasitics.

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- Ensure layouts meet requirements for area, matching, noise, reliability, EM/IR and performance.

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- Work with advanced TSMC technology nodes, including FinFET-based processes.

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- Collaborate with circuit design, verification, reliability, and physical design teams throughout the development cycle.

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- Support IP integration, top-level layout, tapeout activities, and design documentation.

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- Participate in layout reviews and contribute to improving layout methodologies and productivity.

/n /n Required Qualifications /n /n

- Bachelor's or Master's degree in Electrical/Electronics Engineering, VLSI, or related field.

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- 4–10 years of hands-on experience in Analog/Mixed-Signal IC Layout.

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- Strong experience in full-custom analog layout.

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- Hands-on experience with TSMC technology nodes is required.

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- Experience in advanced technology nodes, preferably 16nm and below, will be highly preferred.

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- Strong understanding of:

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- Analog layout fundamentals

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- Device matching

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- Parasitic effects

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- Analog routing techniques

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- Noise isolation

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- Reliability considerations

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- Strong experience with DRC/LVS/ERC and physical verification.

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- Experience with PEX and post-layout simulation/debugging.

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- Ability to independently take blocks from schematic → layout → verification → tapeout.

/n /n Tools & Technology /n Preferred tools: /n /n

- Cadence Virtuoso

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- Cadence Layout XL

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- Calibre

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- PVS / Assura

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- StarRC / Quantus or equivalent extraction tools

/n /n Technology: /n /n

- TSMC CMOS / FinFET nodes

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- Preferably TSMC 16nm, 12nm, 7nm, 5nm and below

/n /n Preferred Experience /n Candidates with experience in layout for the following will be preferred: /n /n

- SerDes PHY

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- DDR / LPDDR PHY

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- High-speed I/O

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- PLL / DLL / CDR

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- ADC / DAC

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- Power Management ICs

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- Data converters

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- Precision analog blocks

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- High-speed analog/mixed-signal circuits

/n /n Experience with high-speed interface PHYs and advanced FinFET nodes will be an added advantage. /n Key Competencies /n /n

- Strong analog layout fundamentals

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- Excellent device-matching expertise

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- Advanced-node layout experience

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- Parasitic-aware design

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- Physical verification/debugging

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- Strong schematic-to-layout understanding

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- Ability to work independently

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- Good collaboration with circuit designers and verification teams

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- Tapeout experience

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📌 Analog Layout Engineer (Bengaluru)
🏢 leadIC Design
📍 Bengaluru