Job DescriptionWho are we and what do we do?

NThe HVP team in TI develops power solutions for a wide array of end-equipments, with several hundreds of volts of withstand capability. This team in TI offers one of the world's largest comprehensive portfolios of high-performance AC/DC and isolated DC/DC controllers, GaN-integrated power-stages and converters, and modules with the widest range of power topology options.

NThis is a new investment area for TI in India, and the candidate will get to be part of an exciting startup-like ecosystem, getting the experience of building a team and technical expertise under the safety of the wider TI umbrella.

NWhat will you be doing inthis role? (Responsibilities)

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- Responsible to develop detailed coverage driven Verification plan working closely with System and design team.
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- Behavioral Modelling ofanalog blocks using SV RNM, verilogAMS (wreal, electrical).
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- Identify and develop system level tests in AMS to ensure bug free silicon.
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- Independently develop SV/UVM based testbenches, tests, checkers, assertions and enhancing with randomization and coverage.
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- Innovate & drive new and improved design verification methodologies as needed, work with the EDA team to upgrade tools and flows.
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- Interacting with Test/Validation in various post silicon activities and customer debug/analysis.
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- Team player: Collaborate and drive smart initiatives within the team. Mentor and lead the junior folks in team
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- Closely working with DMS/DV team to understand the SOC – RTL verification and capable to support in case of project requirement.
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- Good interaction with Digital Design team, Firmware developers, Analog Designers, and rest of the team.
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nWhat do we expect from you? (Mini Qualifications)





NKnowledge and Skills

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- Robust fundamentals in mixed-signal designs, including a thorough understanding of analog building blocks, digital design processes, and top-level integration.
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- Experienced in developing mixed signal testbench in SV/UVM from scratch with the capability to debug and optimize mixed-signal simulation performance, understanding the necessary trade-offs.
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- Strong simulation debugcapability, able to analyze simulation waveforms and pinpoint issues in schematics simulation or models
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- Knowledge on analog controllers to develop system testbench and debug issues.
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- Handling & owning design deliverables and schedule
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- Bachelors / Masters in Electrical / Electronics Engineering
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nOther

nGoodteam player, attitude and thirst for continuous learning

NStrong communication and interpersonal skills

NAbility to function independently, be self-driven

NPreferred Skills/ Experience

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- 3-10 years of experience in mixed-signal design verification
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- Hands on experience/expertise in working with SOC and developing SOC-AMS testbench.
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- Expertise in developingthe simulation/DV plan as per the system definition.
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- Experience with CadenceMixed-Signal Design Environment tools, including Virtuoso, ADE Assembler, Xcelium, VIVA & Simvision
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- Expertise in Cadence Spectre simulation test bench development, Regression Flow & debug
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- Expertise in mixed-signal waveform review, debugging, and coverage analysis.
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- Excellent with HDL – system Verilog, UVM, verilogAMS
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- Experience in writing checkers, assertions and monitors for top-level simulations.
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- Expertise in automationusing Python / Perl / Tcl / shell scripting.
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- Experience as AMS Lead for a project is an addon.
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📌 Ams-Dv Lead | High-Voltage Power (Karnataka)
🏢 Texas Instruments
📍 Karnataka