Principal SoC Design Lead

Job Summary

Introduction: The Principal SoC Design Lead is responsible for the architecture, microarchitecture, integration, and delivery of complex SoCs for Smart Analog Sensor products. This individual serves as the technical leader for one or more SoC programs, driving IP integration, subsystem development, RTL quality, and cross-functional execution from concept through silicon.

The role requires robust expertise in processor-based SoCs, subsystem architecture, RTL development, and SoC integration, combined with the ability to lead technical teams across multiple disciplines.

We are seeking seasoned SoC Design / RTL Lead who combines strong architectural vision with deep hands-on RTL experience. The successful candidate will play a pivotal role in defining and delivering next-generation platform architectures that enable multiple customer products and future derivatives.

Join us and put your skills, insight, and passion to redefine what's possible.

Key Responsibilities

- Definition and ownership of SoC architecture spanning processing subsystems, memory hierarchy, NoC/interconnect, clocking, reset, interrupt and event infrastructure, interfaces, and peripherals.
- Development of microarchitectural specifications from architectural exploration through implementation-ready design specifications
- Ownership of system-level performance, power and area tradeoffs
- Definition and integration of subsystem interfaces across compute, datapath, safety, security, software and peripheral domains
- Technical leadership of RTL implementation teams and convergence of architecture into production-quality RTL
- Collaboration with verification, DFT and physical design teams to achieve project objectives
- Contribute to platform roadmaps and reusable SoC architectures
- Review microarchitecture and RTL implementation of critical blocks.
- Drive issue resolution across architecture, RTL, DV, DFT,



and Physical Design teams.
- Evaluate, select, and integrate internal and third-party IP and establish IP reuse methodologies
- Drive closure of functionality, timing, power, and integration objectives.
- Support post-silicon debug and root-cause analysis.
- Mentor RTL and integration engineers.
- Lead technical reviews and design signoffs.
- Influence engineering methodology and best practices across the organization.

SoC Architecture Planning

- Define SoC and subsystem architectures aligned with product requirements.
- Drive hardware partitioning across processors, accelerators, memories, and peripherals.
- Lead architecture tradeoff analyses covering performance, power, area, safety, and scalability.
- Contribute to platform roadmaps and reusable SoC architectures.

RTL Integration Leadership

- Lead development of complex RTL subsystems and top-level integration.
- Define SoC integration methodologies and quality standards.

IP Strategy

- Evaluate, select, and integrate internal and third-party IP.
- Establish IP reuse methodologies across multiple product generations.
- Ensure robust SoC assembly and subsystem interoperability.

Silicon Execution

- Lead execution from specification through tapeout and silicon bring-up.

Technical Leadership

Minimum Qualifications

- Minimum BS and 15+ years of relevant industry experience
- Experience architecting and delivering complex SoCs
- Experience with memory hierarchies, NoCs, bus architectures and system integration
- Expertise in RTL development using Verilog or SystemVerilog

Preferred Qualifications

- Experience with automotive or safety-critical systems
- Experience with multicore systems

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

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