Job Description

LTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned.

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8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification

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8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies

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Experience in development of UVM based verification environments from scratch

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Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle

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Experience with verification of ARM/RISC-V based CPU sub-stems or SoCs

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Experience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet

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Experience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments

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Experience with revision control stems like Mercurial(Hg), Git or SVN

📌 Senior DV Engineers (UVM/Verliog) (Bengaluru)
🏢 L&T Technology Services
📍 Bengaluru