LEAD BEHAVIORAL MODELING ENGINEER – LATTICE SEMICONDUCTOR INDIA Location: Hyderabad / Pune / Chennai (India) JOB SUMMARY We are seeking a Lead Behavioral Modeling Engineer to join Lattice Semiconductor's FPGA Architecture & Design team. You will lead development of behavioral and architecture models for next-generation low-power FPGA fabrics, own power and timing characterization, and mentor a small modeling team. This is a technical leadership role focused on modeling methodology and design optimization—not traditional product RTL design or verification.

KEY RESPONSIBILITIES - Develop and maintain behavioral models for FPGA fabric elements (CLBs, routing, interconnects, logic blocks) - Own power and timing characterization across PVT (Process, Voltage, Temperature) corners - Build Python-based automation flows for rapid design exploration and PPA analysis - Lead modeling methodology improvements and drive continuous optimization - Collaborate with architecture, RTL, and circuit design teams to validate design intent - Mentor and guide modeling engineers on best practices and technical excellence - Correlate behavioral models against silicon measurements and real chip data - Establish and communicate modeling standards and documentation REQUIRED QUALIFICATIONS - Bachelor's degree in Electrical Engineering or related field (Master's preferred) - 8+ years in behavioral/architecture modeling or FPGA/ASIC design - 2+ years of technical leadership experience - Proficiency in C++, SystemC,



and Python for model development - Deep knowledge of FPGA fabric architecture (CLBs, LUTs, routing, interconnects) - Strong understanding of power and timing characterization methodologies - Excellent problem-solving and technical communication skills - Ability to lead cross-functional teams and drive cooperative efforts PREFERRED QUALIFICATIONS - Master's degree (M.Tech, MS) in Electrical/Computer Engineering - Prior experience at semiconductor companies - Published papers or patents in FPGA modeling or architecture optimization - Experience with ML-based power prediction or on-die sensor integration - Test-chip bring-up and silicon validation experience WHAT YOU WILL NOT BE DOING This role is NOT focused on:

- Verilog/VHDL/SystemVerilog code development for product design - SystemVerilog testbench and formal verification - Gate-level or post-layout simulation - Traditional Design Verification (DV) - Physical design (place & route, floorplanning) If your background is primarily RTL design or DV, this may not be the right fit. WHY LATTICE SEMICONDUCTOR? Lattice is the global leader in low-power FPGA solutions for edge AI, automotive, aerospace, and IoT. Your modeling work directly impacts next-generation FPGA architectures and time-to-market for innovative products.

We offer

- Deep technical challenge and leadership opportunity - Collaborative, innovation-driven culture - High-impact products used globally - Competitive compensation and benefits

📌 LEAD BEHAVIORAL MODELING ENGINEER - LATTICE SEMICONDUCTOR INDIA (Hyderabad)
🏢 Lattice Semiconductor
📍 Hyderabad