Job DescriptionLocation: Greater Bengaluru Area (Hybrid)/ Greater Hyderabad
Nhttps://www.Thecube.Net/events/nyse/ai-factory-data-center-of-the-future/content/Videos/d1ad8af3-1424-4336-a9b3-1d02b5a354b4
Nwe are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.
NOur proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.
Nour architecture is not just an incremental improvement — it's a foundational shift in how AI hardware is built for the future.
N. Location: Hyderabad/Bangalore
NSenior Principal Digital Design Engineer — PCIe/CXL
N__________________________________________________________________________________________
NAbout Kandou AI
nKandou AI is powering the future of AI infrastructure, operating at the intersection of information theory and semiconductor design. Kandou pioneered Copper MIMO (Chord Signaling) technology, transforming crosstalk and noise inherent in copper links into a mechanism that unlocks higher bandwidth, lower power, and greater scale for GPU, memory, network, and rack-scale connectivity. The company's product portfolio includes the Matterhorn USB4 Retimer, Regli PCIe Retimer, Zetti PCIe Switch, and Glasswing Chiplet Interconnect IP, and it is building next-generation AI systems spanning AI inference, CXL memory platforms, and ultra-high-speed scale-up/scale-out networking.
NHeadquartered in Lausanne, Switzerland,
Kandou AI has a global engineering footprint including design centers in the United States, United Kingdom, Germany, Taiwan, and a newly established India Chip Design Headquarters in Hyderabad, reflecting continued investment in world-class semiconductor design talent. Kandou fosters a hybrid, adaptable working culture built around autonomy, teamwork, and a shared commitment to pushing the boundaries of connectivity technology.
NResponsibility and Authority
NNo.
nDescription
N1
nOwn and drive PCIe/CXL subsystem micro-architecture definition, RTL implementation, and integration.
N2
nCollaborate closely with Architecture teams to translate requirements into robust RTL designs.
N3
nWork with Design Verification teams on test-plan reviews, debug, and coverage closure.
N4
nPartner with Physical Design and DFT teams to ensure PD-friendly and DFT-ready RTL.
N5
nSupport siliconbring-up and post-silicon debug, working with firmware and validation teams.
N6
nDrive design quality improvements, coding best practices, and reuse across projects.
N7
nParticipate in design reviews, milestone reviews, and cross-functional technical discussions.
N8
nMentor junior designers and provide technical leadership within the PCIe/CXL design domain.
N9
nIndividual responsibilities for this role are defined by Kandou's executive team on a project-by-project basis and may vary from this .
NRequired Competencies — Education
NNo.
nDescription
N1
nMaster's or Bachelor's degree in Electronics/Electrical Engineering (or equivalent), with 18+ years of relevant experience in RTL design.
NRequired Competencies — Experience
NNo.
nDescription
N1
nEnd-to-end PCIe/CXL subsystem RTL design execution and sign-off.
N2
nProven experience delivering complex PCIe/CXL IP or subsystems from architecture through RTL closure.
N3
nStrong hands-onexperience in SystemVerilog / Verilog RTL development.
N4
nExpertise in PCIe protocol architecture, including link, transaction, and PHY interaction layers.
N5
nStrong understanding of CXL.Io, CXL.Cache, and CXL.Mem architectures.
N6
nDeep knowledge of ARM-based SoC integration and AMBA protocols (AXI-4, CHI, ACE).
N7
nExperience designing high-performance, low-latency data paths and handling ordering, coherency, and error mechanisms.
N8
nSolid grasp of clocking, resets, CDC/RDC, low-power techniques, and performance optimization.
N9
nExperience supporting lint, CDC/RDC, synthesis, and design sign-off flows.
NRequired Competencies — Skills
NNo.
nDescription
N1
nProficient in debugging functional and performance issues at subsystem and SoC levels.
N2
nExperience using industry-standard EDA tools from Synopsys, Cadence, and Mentor/Siemens.
N3
nProficient in scripting languages such as Tcl, Perl, or Python.
N4
nExperience withversion control systems such as Git, SVN, etc.
N5
nStrong communication and presentation skills, comfortable interfacing across cross-functional and geographically distributed engineering teams.
NSkils
nCXL
nPCIe
NARM SoC
nSystemVerilog
NVerilog
nMicroarchitecture
NContact
nUday
[email protected]
NMulya Technologies
n"Mining the Knowledge Community"
📌 Hiring: Senior Principal Digital Design Engineer -- Pcie/Cxl (Bengaluru)
🏢 Mulya Technologies
📍 Bengaluru