Key Responsibilities:
Build complex UVM/SystemVerilog testbench components and architectures.
Drive functional and code coverage closure to ensure design robustness.
Collaborate with design teams to debug complex architectural and micro-architectural issues.
Key Requirements & Skills:
Languages & Methodologies: Proficiency in SystemVerilog and UVM (Universal Verification Methodology).
Verification Expertise: Experience in testbench development, constrained-random verification, functional coverage, and code coverage.
Debugging: Solid waveform debugging skills and familiarity with industry-standard simulators (Synopsys, Cadence, or Mentor Graphics).
Domain Knowledge: Understanding of SoC/IP protocols (e.g., AMBA AXI/AHB/APB, PCIe, DDR, etc.) is a solid plus.
📌 Verification Engineer Hyderabad (India)
🏢 Proxelera
📍 India
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