We are looking for a Senior Analog Layout Engineer with robust hands-on expertise in custom/analog layout for advanced technology nodes. The ideal candidate should have experience working on 2nm/3nm/5nm designs and a solid understanding of layout fundamentals, matching, parasitics, and physical verification.
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Key Responsibilities
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Own block-level analog/custom layout from floorplanning to physical verification.
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Develop high-quality layouts for analog, mixed-signal, and custom circuits.
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Work extensively on 2nm/3nm/5nm technology nodes.
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Apply advanced matching, symmetry, common-centroid, shielding, and sensitive-net routing techniques.
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Optimize layouts for PPA, parasitics, IR drop, EM, and signal integrity.
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Perform DRC, LVS, ERC, PEX and resolve physical verification issues.
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Analyze and mitigate RC parasitics and layout-dependent effects (LDE).
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Collaborate closely with Analog Design, Circuit Design, and Physical Design teams.
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Core Technical Skills
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Strong hands-on experience in Cadence Virtuoso / Custom Layout.
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Expertise in advanced-node analog/custom layout — 2nm/3nm/5nm.
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Solid knowledge of FinFET/GAA layout concepts and advanced-node design rules.
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Deep understanding of matching, shielding, guard rings, isolation, and parasitic optimization.
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Proficiency in Calibre/PVS and physical verification flows.
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Experience with PEX and post-layout simulation/correlation.
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Qualifications
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B.E./B.Tech/M.E./M.Tech in ECE/EEE/VLSI or related discipline.
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5–10 years of relevant Analog/Custom Layout experience.
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Proven experience delivering tapeout-quality layouts at advanced technology nodes.
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