Job Description

STA Engineer

n

n

KEY RESPONSIBILITIES:

n

n
Responsible for Multi Voltage domain STA environment setup, execution and timing closure of GPU
n
Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks
n
Ensuring timing correlation between PnR <-> STA and timely feedbacks to PD team
n
Generating block level HS session and using Top context from SoC for Block-SoC Interface timing closure.
n
Generating timing ECO using Tweaker/PrimeClosure.
n

n

n

PREFERRED EXPERIENCE:

n

n
3+ years of experience in timing closure of high frequency blocks like CPU/GPU (> GHz range)
n
Analyzing the timing reports and identifying both design and constraints related issues.




n
Worked on blocks with multiple power and voltage domains
n
Preferred EDA tool experience: Primetime, Tweaker/PrimeClosure, Innovus
n
Robust Understanding of DFT modes requirements for timing signoff
n
Positive understanding of physical design flow and ECO implementation
n
Strong understanding of SDC constraints, OCV,AOCV,POCV analysis
n
Solid TCL/scripting knowledge is mandatory.
n

n

n

ACADEMIC CREDENTIALS:

n

n
Bachelors or Masters degree in Electrical Engineering
n

n

📌 Sta Engineer Bengaluru (India)
🏢 MediaTek
📍 India