Senior DFT Verification Engineer | 5–10 Years
We are looking for experienced DFT Verification Engineers with robust hands-on expertise in Siemens Tessent tools.
Key requirements:
- Strong hands-on experience with Siemens Tessent tools
- Expertise in ICL and PDL development and validation
- Experience in RTL and gate-level DFT verification
- Strong understanding of DFT methodologies and pattern validation
- Knowledge of post-silicon pattern handoff is preferred
- Experience: 5–10 years
Interested candidates can share their updated resumes at
[email protected] as well
Pay: ₹1,325,642.33 - ₹3,521,158.35 per year
Work Location: In person
📌 DFT Engineer (Bengaluru)
🏢 Chiplogic Technologies
📍 Bengaluru