Job DescriptionLead Synthesis Engineer
NLocation: Bengaluru, India
NExperience: 6–12 Years
NAbout the Role
nWe're looking for a Lead Synthesis Engineer to drive RTL-to-Gate implementation for complex SoCs across advanced technology nodes. You'll own synthesis convergence, optimize PPA, and collaborate with RTL, STA, DFT, and Physical Design teams to deliver high-quality silicon.
NWhat You'll Do
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- Drive RTL synthesis using Synopsys Design Compiler/Fusion Compiler. N
- Optimize designs for Power, Performance, and Area (PPA) while meeting timing and design constraints. N
- Develop and debug SDC constraints, synthesis scripts, and automation flows. N
- Analyze timing, area, power, and QoR reports;
resolve synthesis and logical issues. N
- Work closely with RTL, STA, DFT, Physical Design, and ECO teams to achieve implementation closure. N




- Support low-power methodologies, LEC, and synthesis signoff across advanced process nodes. N

nWhat We're LookingFor
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- 6–12 years of experience in ASIC/SoC Synthesis. N
- Solid expertise in Synopsys Design Compiler, Fusion Compiler, TCL scripting, and SDC. N
- Solid understanding of timing constraints, clock gating, UPF, low-power design, LEC, and ECO flows. N
- Experience with advanced technology nodes (7nm/5nm/3nm) is preferred. N
- Strong debugging, problem-solving, and cross-functional collaboration skills. N

nBuild next-generation silicon by delivering world-class synthesis quality across cutting-edge SoCs.

📌 Hiring: Lead Synthesis Engineer (Karnataka)
🏢 Leadsoc Technologies
📍 Karnataka