Job DescriptionQualification: B.E./B.Tech/M.E./M.Tech in ECE, EEE, VLSI or related disciplines
nWhat You'll Be Working On:
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- Block-level and full-chip Static Timing Analysisn
- Development, validation and debugging of SDC constraintsn
- Setup, Hold, Recovery & Removal analysisn
- MCMM timing analysis across PVT cornersn
- Timing closure across multiple design scenariosn
- Root-cause analysis and resolution of timing violationsn
- Clock timing and clock architecture analysisn
- Timing ECOs and implementation changesn
- Timing sign-off and generation/review of timing reportsn
- OCV / AOCV / POCV and derating analysisn
- Signal Integrity / Crosstalk-aware timing analysisn
- Timing closure for high-performance and complex SoC/ASIC designsn

nWhat We're Looking For
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- 6+ years of hands-on STA experiencen
- Robust expertise in Synopsys PrimeTime and/or Cadence Tempusn




- Excellent understanding of STA concepts and timing methodologiesn
- Strong experience with SDC constraintsn
- Good understanding of MCMM, OCV, AOCV & POCVn
- Strong knowledge of clock architecture, clock timing and clock-related issuesn
- Experience with timing ECOs and timing closure methodologiesn
- Good understanding of the ASIC Physical Design flown
- Strong Tcl scripting skillsn
- Python scripting knowledge will be an added advantagen

nGood to Have
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- Full-chip STA and sign-off experiencen
- Experience with advanced technology nodesn
- Exposure to Signal Integrity / Crosstalk analysisn
- Experience with low-power designsn
- Experience working on large and complex SoC designsn

📌 STA Lead (Vasanthanagar)
🏢 leadIC Design
📍 Vasanthanagar