Job DescriptionHiring: Memory Layout Engineers
NExperience: 2–6 Years
NLocations: Bangalore | Noida | Hyderabad
NNotice Period: Immediate Joiners / Short Notice Preferred
NKey Responsibilities:
N
- n
- Hands-on experience in Memory Layout / Custom Layout for SRAM, ROM, NVM or Memory Compiler blocks. N
- Experience in Bitcell, Memory Array, Row/Column Decoder, Sense Amplifier, I/O and Peripheral layouts. N
- Strong knowledge of Floorplanning, Routing, Hierarchical Layout & Layout Optimization. N
- Hands-on experience with DRC, LVS, ERC, Antenna, EM/IR and Physical Verification. N
- Good understanding of CMOS/FinFET technologies, layout rules, matching, parasitics and PPA optimization. N
- Proficiency in Cadence Virtuoso/Virtuoso XL and preferably Calibre. N




- Knowledge of Memory Compiler / Tiling / Automation is an added advantage. N
- Exposure to SKILL / Perl / TCL / Shell scripting is a plus. N

nEducation: BE/B.Tech/M.Tech in ECE, EE, VLSI, Microelectronics or related field.
NIdeal Candidate: Memory/Custom Layout Engineer with robust hands-on implementation and physical verification experience. Current industry postings similarly emphasize Virtuoso, DRC/LVS, memory arrays and physical verification.
NInterested candidates canshare their updated CV with:
NTotal Experience | Relevant Memory Layout Experience | Current Location | Notice Period | Preferred Location

📌 Memory Layout Engineer (Karnataka)
🏢 Leadsoc Technologies
📍 Karnataka