Job DescriptionStatic Timing Analysis (STA) Lead
nJoin the India team of most cutting-edge and well-funded storage startup in Silicon Valley as the Lead STA Engineer working on timing closure of complex high performance ASIC in latest technology nodes.
nAs a STA lead you will be working on PrimeTime based flow development and timing closure of multi-million gate SoC design for all modes and all corners in 16/12/7/5nm processes.
nLocation: Bangalore, KA. India
nQualification and Skillset Requirements
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- Minimum BE/BS degree (Masters preferred) in Electrical/Electronics Engineering/VLSIn
- 10+ years of practical experience in Static Timing Analysis (STA) using Primetimen
- Robust fundamentals in digital ASIC designn
- Understanding of SoC design and implementation methodology and challengesn
- Understanding of one or more of design flows like Synthesis, Constraint development and STA (Functional and DFT modes)



and Physical Designn
- Good hands on expertise with industry standard implementation tools like – Synopsys PrimeTime, Design Compiler/Fusion Compiler etc. for block as well as top leveln
- Able to work with TCL and Perl scripting and flow automationn
- Excellent communication and team workn

nRoles And Responsibilities
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- Work on STA methodology and flow developmentn
- Develop and integrate constraints at block and SoC leveln
- Provide early feedback on design/timing issues and solutionsn
- Work with Backend team for timing closure during PnRn
- Work with IP and SoC Design team in optimizing the design to meet timingn
- Work on timing closure for block/top, all modes/corners by providing timing ECOs etc.n

📌 Static Timing Analysis (Vasanthanagar)
🏢 ScaleFlux
📍 Vasanthanagar