12 Sep
|
Mirafra Technologies
|
Karnataka
12 Sep
Mirafra Technologies
Karnataka
Experience : 3 Years Notice Period : Immediate to 30 days. Job Description: * Placement/Power aware synthesis using Synopsys & Cadence tools (DCG/NXT/FC, Genus) * Constraints development, Formal Verification, CECO, Static Timing Analysis & timing closure * Work closely with design team to come up with preplacement requirements & timing constraints * Work closely with physical design team for floorplan, placement & timing reviews * Work closely with cross-functional teams to review standard cell profile, timing models & memory models Skills: * Good understanding of ASIC design flow * Hands on experience in synthesis and static timing analysis * Proficiency with Synopsys DC & PT tools and Verilog/VHDL is a must Experience in Perl, TCL and shell scripting is desirable * Excellent interpersonal & analytical skills with ability to work independently Bachelors or Master's Degree with a robust VLSI Background
📌 Synthesis Engineer (Karnataka)
🏢 Mirafra Technologies
📍 Karnataka