Job Title: Physical Design Engineer

Location : Bengaluru

J ob Summary:

We are looking for a skilled Physical Design Engineer with experience in ASIC/SoC implementation from synthesis to GDSII. The candidate will be responsible for driving the physical design flow, ensuring timing, power, area, and quality targets are achieved while meeting project schedules.

Key Responsibilities:

- Perform end-to-end physical design activities, including:
- Floorplanning
- Power planning
- Placement
- Clock Tree Synthesis (CTS)
- Routing
- Physical verification
- Timing closure
- Analyze and fix setup/hold timing violations.
- Perform static timing analysis (STA) and timing signoff.
- Conduct IR drop, electromigration (EM), and power integrity analysis.
- Resolve DRC, LVS, and antenna violations.
- Collaborate with RTL, DFT, STA,



and verification teams for design closure.
- Optimize design for performance, power, and area (PPA).
- Support tape-out activities and signoff requirements.
- Develop scripts for design automation and flow enhancement.

Required Skills:

- Robust understanding of ASIC/SoC physical design flow.
- Experience with industry-standard EDA tools such as:
- Cadence Innovus
- Synopsys ICC2
- PrimeTime
- Tempus
- Calibre
- Knowledge of:
- Timing constraints (SDC)
- STA concepts
- Multi-mode Multi-corner (MMMC)
- Low-power methodologies (UPF/CPF)
- Good understanding of semiconductor process technologies (7nm/10nm/16nm/28nm and above).

📌 Physical Design Engineer (Bengaluru)
🏢 UST
📍 Bengaluru