We are hiring For Design Verification and GLS Engineer
Exp: 4 to 12 Years
Np: Immediate to 30 days
Key skills: UVM, SV, Verilog, High speed protocols and Power Management (Plus advantage)
Key Responsibilities
- Develop directed and constrained-random testcases
- Debug failures and root-cause issues across RTL, testbench, and tools
- RTL as well as Gate level simulations
- Automate regression flows and improve verification productivity
Required Skills & Qualifications
Technical Skills
- Good knowledge of SystemVerilog
- Hands-on experience with UVM (Universal Verification Methodology)
- Experience with EDA tools (e.g., VCS, Verdi)
- Experience in debugging RTL and gate level simulation issues
- Valuable knowledge of PCIe protocol
Programming/Scripting
- Proficiency in Python/Perl/Shell scripting for automation
📌 Hiring For Design Verification Engineer (Bangalore Metropolitan Area)
🏢 Tech Mahindra
📍 Bangalore Metropolitan Area
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