Technical Lead - Design Verification /n /n Experience: 8+ Years /n Location: Bengaluru /n /n We are seeking a highly skilled and experienced Senior Design Verification Engineer to join our SoC/ASIC verification team in Bangalore. The ideal candidate will have a deep understanding of the verification lifecycle, from test planning to coverage closure, and be able to independently drive complex verification tasks for IP, subsystem, or full-chip level designs. /n /n Key Responsibilities: /n /n
Develop and execute test plans for IP/subsystem/full-chip level verification.

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Build and maintain constrained-random and directed testbenches using SystemVerilog and UVM.

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Drive functional coverage closure and ensure high-quality tape-outs.

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Collaborate with RTL designers, architecture, and software teams to understand design features and define test scenarios.

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Participate in code reviews , debug RTL/testbench issues, and file bug reports.

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Use industry-standard tools like VCS, QuestaSim, Verdi, Synopsys, Cadence, or Mentor toolchains.

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Mentor junior team members and lead small verification teams or projects when required.

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Support post-silicon validation teams and participate in bring-up/debug if necessary.

/n /n /n Required Skills and Qualifications: /n /n
B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or related field.

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8+ years of experience in ASIC/SoC design verification.

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Solid expertise in SystemVerilog , UVM , and object-oriented programming .

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Proven track record in building and maintaining verification settings from scratch.

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Experience in assertion-based verification , coverage analysis , and debug tools .

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Solid understanding of digital design concepts , SoC architecture , and protocols like AMBA (AXI, AHB), PCIe, USB, or DDR.

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Hands-on experience with simulation tools , waveform viewers , and version control systems (Git, Perforce, etc.) .

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Excellent problem-solving, communication, and team collaboration skills.

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📌 Staff Engineer Bengaluru
🏢 ACL Digital
📍 Bengaluru