Job DescriptionJob Title: IO Layout Engineer

NExperience: 3+ Years

NLocation: Bangalore

NEmployment Type: Full-time

NIndustry: Semiconductors / ASIC / VLSI / IO & ESD Design

NJob Summary:

NWe are looking for a highly motivated and experienced IO Layout Engineer to join our custom layout team. The candidate will be responsible for full-custom layout of IO cells, ESD protection structures, and high-voltage interfaces for ASIC/SoC applications in deep submicron and FinFET technologies.

NKey Responsibilities:

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- Perform transistor-level custom layout of various types of IO cells including:
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- Standard IOs (CMOS, LVTTL, LVCMOS, SSTL, HSTL)
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- High-speed and specialty IOs (DDR, USB, PCIe, HDMI, etc.)
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- ESD structures, pad rings, and protection circuits
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- Work closely with IO circuit designers to interpret schematics and design intent.
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- Ensure robust layout practices for:
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- ESD compliance
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- Latch-up prevention
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- Electromigration (EM)
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- Voltage isolation and guard ring planning
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- Ensure layout meets foundry-specific DRC, LVS, and antenna rules.
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- Run and close physical verification (DRC, LVS, ERC, ANT) using industry-standard tools.
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- Participate in floorplanning of IO ring and integration with analog/digital blocks.
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- Coordinate with packaging, ESD, and reliability teams to support silicon tapeout.
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nRequired Skills and Experience:

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- B.E/B.Tech or M.E/M.Tech in Electronics, Electrical Engineering, or VLSI.
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- 3+ years of hands-on experience in IO and/or ESD layout.
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- Robust understanding ofESD protection concepts and latch-up avoidance.
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- Expertise in Cadence Virtuoso for layout design and implementation.
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- Experience with DRC/LVStools (Calibre, Assura, PVS).
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- Familiarity with advanced process technologies (28nm, 16nm, 7nm, FinFET, etc.).
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- Good knowledge of layout-dependent effects (LDE), IR drop, and reliability constraints.
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- Attention to detail andstrong debugging/problem-solving skills.
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nPreferred Qualifications:

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- Experience in high-voltage or multi-voltage IO layout (1.8V/3.3V/5V interfaces).
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- Experience with IO ringplanning and integration in complex SoC floorplans.
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- Familiarity with power grid design, bump/ball map coordination, and ESD co-design.
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- Scripting experience inSKILL, Tcl, or Python for layout automation.
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nInterested can share Cv to [email protected]

📌 Io Layout Engineer (Bengaluru)
🏢 ACL Digital
📍 Bengaluru