Job DescriptionSenior Memory Layout Engineer
nLocation: Hyderabad, India
nExperience: 5–10 Years
nRole Overview:
nWe are looking for experienced Senior Memory Layout Engineers with strong hands-on expertise in custom layout and physical implementation of memory circuits. The role involves working closely with circuit design, technology, and verification teams to deliver high-quality, DRC/LVS-clean memory layouts.
nKey Responsibilities:
n
n
Develop custom layouts for memory circuits including SRAM, ROM, Register File, and memory periphery.n
Execute block-level and full-memory layout from schematic/netlist to DRC/LVS-clean database.n
Work on layout of bitcells, sense amplifiers, pre-charge circuits, decoders, write/read paths, and peripheral circuits.n
Perform matching, symmetry, shielding, common-centroid, and parasitic-aware layout as applicable.n
Debug and resolve DRC, LVS, ERC, antenna, density, and connectivity issues.n
Collaborate with circuit designers on layout optimization, PPA, matching, and parasitic reduction.n




Support PEX and post-layout simulation activities.n
Ensure adherence to foundry PDK, design rules, and layout methodologies.n
Participate in design reviews, tapeout activities, and continuous layout methodology improvements.n

nRequired Skills:
n
n
5–10 years of relevant experience in Memory / Custom IC Layout.n
Strong hands-on experience with SRAM and/or memory macro layout.n
Positive understanding of CMOS layout concepts, device matching, parasitics, and design rules.n
Experience with industry-standard tools such as Cadence Virtuoso, Calibre, or equivalent.n
Robust expertise in DRC/LVS debugging and physical verification.n
Understanding of FinFET/advanced-node layout concepts is preferred.n
Good scripting/automation exposure using SKILL, Python, Tcl, or Shell is an advantage.n
Solid analytical, debugging, and cross-functional collaboration skills.n

nPreferred
n
n
Experience with

📌 Senior Memory Layout Engineer Hyderabad
🏢 leadsoc technologies
📍 Hyderabad