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- Experience: 4–10 Years
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- Location: Bengaluru
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- Employment Type: Full-Time
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nAbout the Role

nWe are looking for an experienced Memory / Custom Layout Engineer to join our semiconductor design team and work on advanced SRAM, ROM, NVM and memory compiler designs.

NThe ideal candidate will have strong hands-on experience in full-custom memory layout, including bitcells, memory arrays, row/column decoders, sense amplifiers, I/O and peripheral circuits. The role will involve working closely with circuit design, physical verification and technology teams to develop high-quality, area-efficient and silicon-ready layouts in advanced CMOS/FinFET technologies.

NKey Responsibilities

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- Develop full-custom layouts for SRAM, ROM, NVM and memory compiler blocks.
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- Perform hands-on layoutimplementation of Bitcells, Memory arrays, Row and column decoders, Sense amplifiers, I/O circuits, Peripheral circuits, Control and supporting logic
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- Perform floorplanning, placement and routing for complex memory blocks.
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- Develop hierarchical layouts and optimize layouts for area, performance, power and manufacturability.
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- Apply advanced layout techniques for matching, symmetry, parasitic reduction and noise isolation.
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- Analyze and optimize layout considering design rules, device characteristics and technology requirements.
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- Perform physical verification including DRC, LVS, ERC, Antenna, EM/IR
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- Debug physical verification issues and work with circuit/physical design teams to resolve them.
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- Support post-layout extraction and parasitic-aware optimization.
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- Work closely with circuit designers to understand layout-critical requirements and achieve desired PPA targets.
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- Support block-level andtop-level memory integration and tapeout activities.
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- Contribute to layout methodology, automation and productivity improvements.
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nRequired Skills & Experience

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- Bachelor's or Master's degree in ECE, EE, VLSI, Microelectronics or a related field.
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- Strong hands-on experience in Memory Layout / Custom Layout.
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- Experience with one or more of SRAM, ROM, NVM, Memory Compiler
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- Strong understanding ofmemory architecture and physical implementation.
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- Hands-on experience with bitcell and memory array layout.
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- Experience with layout of decoders, sense amplifiers, I/O and peripheral circuits.
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- Strong knowledge of Floorplanning, Placement & routing, Hierarchical layout, Layout optimization, Matching, Parasitics, PPA optimization
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- Experience with CMOS and/or FinFET technology nodes and advanced layout rules.
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- Solid hands-on experience with DRC, LVS and physical verification.
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- Experience with ERC, Antenna and EM/IR analysis.
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- Proficiency in Cadence Virtuoso / Virtuoso XL.
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- Experience with Calibreor equivalent physical verification tools.
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nGood to Have

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- Experience with Memory Compiler development.
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- Knowledge of memory tiling and array assembly.
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- Experience with layout automation and productivity tools.
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- Scripting experience using Perl/TCL/Shell
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- Experience working on advanced-node memory designs, particularly FinFET technologies.
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- Exposure to memory characterization, silicon bring-up or memory IP integration.
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nIdeal Candidate

NThe ideal candidate is a Memory / Custom Layout Engineer with strong hands-on experience in implementing complex memory structures from schematic/netlist through layout, physical verification and tapeout.

NCandidates who have worked specifically on SRAM bitcells, large memory arrays, memory compilers or advanced-node memory IPs will be strongly preferred.

📌 Hiring: Memory Layout Engineer (Bengaluru)
🏢 leadIC Design
📍 Bengaluru