n
- Test architecturedefinition.
N
- Identifying and implementing RTL changes for DFT.
N
- Performing scan insertion, LEC checks, low power CLP checks.
N
- Developing timing constraints for test mode timing closure.
N
- Scan and ATPG for different fault models.
N
- Boundary scan, ACJTAG, IEEE 1500 implementation and verification.
N
- IEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests.
N
- Running zero delay and timing simulations and debugging on all the above aspects.
N
- Supporting post siliconbring up.
N
- Interacting with customers on DFT aspects and support Marketing & Pre-Sales team.
N
- Experience working on very high speed and low power designs
N
📌 Hiring: Lead Dft Design Engineer (Bengaluru)
🏢 Cadence System Design and Analysis
📍 Bengaluru
Reply to this offer
Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.