Job DescriptionJob Description DV Positions:

NDefine and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification

NDevelop functional tests based on verification test plan

NDrive Design Verificationto closure based on defined verification metrics on test plan, functional and code coverage

NDebug, root-cause and resolve functional failures in the design, partnering with the Design team

NQualifications and Skillsfor DV Positions:

NBachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience

N8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification

N8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies





NExperience in developmentof UVM based verification environments from scratch

NExperience in architecting and implementing Design Verification infrastructure and executing the full verification cycle

NExperience with verification of ARM/RISC-V based CPU sub-stems or SoCs

NExperience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, Ethernet

NExperience in E tools andscripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments

NExperience with revision control stems like Mercurial(Hg), Git or SVN

📌 Asic Design Verification (Bengaluru)
🏢 Lu0026T Technology Services
📍 Bengaluru