Job Description

Analog Layout Engineer

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Required Qualifications:

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Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
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4+ years of experience in analog layout design with a focus on TSMC 7nm, 5nm, and 3nm process technologies.
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Proficiency with Cadence Virtuoso, Mentor Graphics, Synopsys IC Compiler, or equivalent analog layout tools.
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Hands-on experience with TSMC PDKs and process technologies for 7nm, 5nm, and 3nm nodes.
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Solid knowledge of analog circuit design principles, including transistor-level design, biasing, signal integrity, and noise analysis.
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Extensive experience with DRC, LVS, parasitic extraction, and layout verification using tools such as Calibre and ICValidator.
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In-depth knowledge of FinFET, SOI, and other advanced semiconductor process technologies at sub-7nm nodes.
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Ability to optimize analog layouts for PPA (performance, power, area).
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Experience with low-power design techniques in advanced process nodes.
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Familiarity with high-performance analog designs and layouts in 7nm, 5nm, and 3nm technologies.
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Robust problem-solving skills and ability to troubleshoot and resolve layout issues.
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Preferred Qualifications:

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Experience with mixed-signal layouts (analog and digital) for full-chip designs.
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Familiarity with RF layout techniques for high-frequency analog circuits.
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Experience in working with multiple layout design settings (e.g., Virtuoso, IC Studio, Synopsys Custom Compiler).
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Knowledge of electromagnetic interference (EMI), signal integrity, and high-speed layout techniques in advanced nodes.
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Exposure to full-custom layout techniques for complex analog IC designs.
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Understanding of advanced packaging technologies and their impact on analog layout design.
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Experience with statistical analysis tools for yield and design optimization.
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Location: Bangalore

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Experience: 4 to 8 Years

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📌 Analog Layout Engineer Bengaluru (India)
🏢 ACL Digital
📍 India