Qualification

B.E./B.Tech/M.E./M.Tech in ECE, EEE, VLSI or related disciplines

What You'll Be Working On: • Block-level and full-chip

Static Timing Analysis • Development, validation and debugging of

SDC constraints
Setup, Hold, Recovery & Removal analysis
MCMM timing analysis

across PVT corners
Timing closure across multiple design scenarios
Root-cause analysis and resolution of timing violations
Clock timing and

clock architecture analysis
Timing ECOs and implementation changes
Timing sign-off and generation/review of timing reports
OCV / AOCV / POCV

and derating analysis
Signal Integrity / Crosstalk-aware timing analysis
Timing closure for high-performance and complex

SoC/ASIC designs

What We're Looking For 6+ years of hands-on

STA experience Robust expertise in





Synopsys PrimeTime and/or Cadence Tempus Excellent understanding of STA concepts and timing methodologies Strong experience with

SDC constraints Positive understanding of

MCMM, OCV, AOCV & POCV Solid knowledge of clock architecture, clock timing and clock-related issues Experience with timing ECOs and timing closure methodologies Good understanding of the

ASIC Physical Design flow Strong

Tcl scripting skills Python scripting knowledge will be an added advantage

Good to Have
Full-chip STA and sign-off experience
Experience with

advanced technology nodes • Exposure to

Signal Integrity / Crosstalk analysis
Experience with low-power designs
Experience working on large and complex SoC designs

📌 Sta Lead Bengaluru
🏢 Leadic Design
📍 Bengaluru