Job Description

Senior Memory Layout Engineer

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Location: Hyderabad, India

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Experience: 5–10 Years

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Role Overview:

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We are looking for experienced Senior Memory Layout Engineers with strong hands-on expertise in custom layout and physical implementation of memory circuits. The role involves working closely with circuit design, technology, and verification teams to deliver high-quality, DRC/LVS-clean memory layouts.

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Key Responsibilities:

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Develop custom layouts for memory circuits including SRAM, ROM, Register File, and memory periphery.
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Execute block-level and full-memory layout from schematic/netlist to DRC/LVS-clean database.
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Work on layout of bitcells, sense amplifiers, pre-charge circuits, decoders, write/read paths, and peripheral circuits.
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Perform matching, symmetry, shielding, common-centroid, and parasitic-aware layout as applicable.
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Debug and resolve DRC, LVS, ERC, antenna, density, and connectivity issues.
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Collaborate with circuit designers on layout optimization, PPA, matching, and parasitic reduction.
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Support PEX and post-layout simulation activities.
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Ensure adherence to foundry PDK, design rules,



and layout methodologies.
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Participate in design reviews, tapeout activities, and continuous layout methodology improvements.
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Required Skills:

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5–10 years of relevant experience in Memory / Custom IC Layout.
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Solid hands-on experience with SRAM and/or memory macro layout.
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Valuable understanding of CMOS layout concepts, device matching, parasitics, and design rules.
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Experience with industry-standard tools such as Cadence Virtuoso, Calibre, or equivalent.
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Solid expertise in DRC/LVS debugging and physical verification.
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Understanding of FinFET/advanced-node layout concepts is preferred.
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Good scripting/automation exposure using SKILL, Python, Tcl, or Shell is an advantage.
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Solid analytical, debugging, and cross-functional collaboration skills.
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Preferred

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Experience with high-density memory macros and advanced-node technologies.
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Exposure to full-custom layout, PEX, EM/IR, and reliability checks.
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Experience working in a tapeout-driven semiconductor environment.
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📌 Senior Memory Layout Engineer Hyderabad
🏢 leadsoc technologies
📍 Hyderabad