Job Description

Senior Staff DFT Engineer

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Location: Bengaluru

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Experience: 12–16 Years

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Role Overview

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We are looking for a Senior Staff DFT Engineer with deep hands-on expertise in DFT architecture, implementation, ATPG and silicon bring-up for complex SoC designs.

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Key Responsibilities

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Own DFT architecture and methodology for complex SoC/full-chip designs.
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Drive Scan insertion, ATPG, MBIST, JTAG and test compression implementation.
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Develop and validate DFT specifications, test modes and coverage targets.
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Drive ATPG pattern generation, coverage analysis and fault debug.
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Analyze and resolve DFT timing, test power, coverage and physical implementation issues.
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Collaborate with RTL, Physical Design, STA, Verification and Silicon teams through tapeout and bring-up.
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Develop DFT flows and automation using Tcl/Python/Perl.




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Core Technical Skills

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Robust expertise in Scan, ATPG, MBIST, JTAG, EDT/Test Compression.
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Hands-on experience with Synopsys DFTMAX/TestMAX, TetraMAX or Siemens Tessent.
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Deep understanding of stuck-at, transition, path-delay and memory fault models.
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Robust knowledge of DFT architecture, testability, coverage and test modes.
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Experience with advanced-node SoCs and full-chip DFT signoff.
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Robust scripting, debugging and cross-functional technical leadership.
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Ideal Candidate: A deeply hands-on DFT technical leader capable of owning SoC DFT from architecture through implementation, signoff and silicon bring-up.

📌 Senior Staff Dft Engineer Bengaluru
🏢 leadsoc technologies
📍 Bengaluru