Job Description

Job Title: FPGA RTL Design Engineer

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Location: Bengaluru, India

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Experience: 4+ Years

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Role Overview:

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We are seeking a skilled FPGA RTL Design Engineer with 4+ years of experience in FPGA development and digital design. The candidate will be responsible for RTL design, implementation, verification, and FPGA bring-up for high-performance SoC/FPGA-based solutions.

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Key Responsibilities:

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Design and develop RTL using Verilog/SystemVerilog/VHDL for FPGA-based applications.
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Perform FPGA synthesis, place & route, timing closure, and performance optimization.
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Develop and execute functional verification plans, testbenches, and debugging activities.
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Collaborate with hardware, firmware, and system teams for integration and validation.
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Analyze and resolve design, timing, and FPGA implementation issues.
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Support board bring-up, lab validation, and customer issue resolution.
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Required Skills:

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4+ years of experience in FPGA RTL design and verification.
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Robust proficiency in Verilog/SystemVerilog and digital design fundamentals.
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Experience with FPGA tools such as Xilinx Vivado, Intel Quartus, or equivalent.
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Valuable understanding of timing analysis, CDC, reset synchronization, and FPGA architectures.
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Experience with simulation and debugging tools (ModelSim, Questa, VCS, etc.).
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Familiarity with interfaces such as PCIe, Ethernet, DDR, AXI, SPI, I2C, or UART.
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Robust problem-solving and debugging skills.
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📌 Fpga Rtl Design Engineer Bengaluru
🏢 UST
📍 Bengaluru