Location: Noida, Bangalore & Hyderabad

Experience: 2-8 years

Availability: Immediate Joiners Only

Job Description

We are seeking a solid Digital Physical Design Engineer to drive block-level physical implementation of complex So Cs/ASICs across advanced nodes.

The role involves hands-on execution and ownership of key blocks from synthesis to tape-out, ensuring closure across timing, power, area, and signoff quality, while collaborating with cross-functional teams and contributing to flow improvements.

Responsibilities
Execute physical design activities including floor planning, power planning, placement, CTS, routing, and STA for assigned blocks Drive timing closure across multi-mode, multi-corner scenarios Perform physical verification (DRC, LVS, Antenna) and resolve violations to achieve clean signoff Conduct power integrity analysis (IR drop, EM) and support PDN optimization Support DFT implementation and ensure proper test structure integration Analyze and debug timing, congestion, power,



and signal integrity issues Execute ECOs and support tape-out readiness under tight schedules Develop and use automation scripts to improve flow efficiency Contribute to methodology improvements and standardization efforts Collaborate with team members on implementation strategies, constraints, and floorplans Qualification
Bachelor's or Master's degree in Electronics / Electrical Engineering or related field 2–6 years of hands-on experience in digital physical design of So Cs or ASICs Proficiency with industry-standard EDA tools (Fusion Compiler / Innovus / ICC2, Tempus / Prime Time, Voltus / Red Hawk, Calibre) Solid understanding of: ○ Floorplanning and power planning basics ○ Placement and routing optimization ○ Clock tree synthesis (CTS) ○ Static Timing Analysis (STA) and timing closure techniques ○ Physical verification and reliability checks Exposure to advanced nodes (16nm / 7nm / 5nm preferred) Solid scripting skills (Tcl required; Python/Perl preferred) Soft Ski

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