Job DescriptionPrimary purpose of the role
NThe role involves taking existing FPGA design documentation, signal-mapping sheets and Proto-1 hardware from partially drafted specifications through to a working, timing-clean and system-validated FPGA implementation. The position will develop high-speed data-processing pipelines, interface with ADCs, DACs and communication peripherals, implement robust clock-domain and reset architectures, and collaborate closely with Hardware, Embedded Software and Application teams.
NThis is a hands-on individual contributor role requiring solid expertise in VHDL, AMD Xilinx FPGA architecture, Vivado, high-speed data acquisition, timing closure, CDC, LVDS interfaces and hardware debugging.
NMajor responsibilities:
N
- n
- RTL Design & FPGAImplementation N
- Clocking, CDC & Reset Architecture N
- High-Speed LVDS & Data Capture N
- Timing Closure & FPGA Optimisation N
- Verification & Validation N
- Hardware Bring-Up & Debugging N
- FPGA Configuration & Release Management N
- Cross-Functional Collaboration N
- Documentation & Design Governance N

📌 Field-Programmable Gate Arrays Engineer (Alibag)
🏢 Metal Power Analytical
📍 Alibag