13 Sep
|
MAXVY
|
Bengaluru
Location : Bangalore
Experience : Fresher
Education : B.E, M.E, M.Tech, B.Tech
Role :
- Required Skill:
- Strong knowledge of Verilog coding based on design concepts and timing diagram.
- Solid understanding of Digital Electronics fundamentals.
- Basic knowledge of AMBA protocol.
Job Description :
We are looking for a passionate and motivated RTL Intern to join our CSI Project team.
Salary : Unpaid
📌 RTL Intern (CSI /C Master) (Bengaluru)
🏢 MAXVY
📍 Bengaluru