Achieve timing closure across all modes and corners.
Resolve DRC, LVS, ERC and signoff violations.
Handle lowpower design techniques:
- MultiVt, Multivoltage (UPF)
- Power gating, clock gating
Perform physical verification and signoff:
- STA (Primetime)
- SI / Crosstalk
- IR drop & EM analysis
Work on advanced nodes (7nm, 5nm, 3nm or below)
Collaborate with:
- RTL & Microarchitecture teams
- DFT & Test engineers
- Foundry and CAD teams
Debug complex timing, congestion, power, and variability issues.
Drive methodology improvements and automation (scripts/flows).
Key Responsibilities
1. Design and architect large-scale physical design solutions utilizing tools such as Cadence and Synopsys, ensuring scalability, performance, and security throughout the design process.
2. Lead training initiatives and knowledge transfer sessions to develop team capabilities in physical design, ensuring a high level of proficiency within the team and minimizing delivery risks.
3.
Continuously evaluate and adopt cutting-edge physical design technologies and methodologies to deliver high-quality, future-proof solutions that meet client expectations and industry standards.
4. Utilize domain expertise in physical design to gather and analyze client requirements, delivering tailored solutions and crafting a technology strategy that aligns with overarching business goals.
Skill Requirements
1. Expert proficiency in physical design tools such as Cadence Innovus and Synopsys IC Compiler.
2. Solid understanding of semiconductor design principles and methodologies including RTL to GDSII flow.
3. Excellent problem-solving skills with the ability to architect solutions for complex design challenges.
4. Proficient in scripting languages such as Tcl and Python for automation in physical design tasks.
Other Requirements
1. Certification in advanced physical design techniques is optional but valuable.
2. Certification in relevant industry standards (e.g., IEEE, ISO) is a plus.