Senior DFT Design/Micro architect Engineer, Google Cloud

Location: Bengaluru, Karnataka, India
Experience Level: Mid

As a Senior DFT Design/Micro Architect Engineer at Google Cloud, you will have the prospect to shape the future of AI/ML hardware acceleration. You will work on cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. Your contributions will impact the innovation behind products loved by millions worldwide, leveraging your design and verification expertise to verify complex digital designs with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Minimum Qualifications:

- Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
- 8 years of experience in the implementation and validation of DFT technologies.
- Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.
- Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.
- Experience in leading DFT activities throughout an ASIC development flow.

Preferred Qualifications:

- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, or a related field.
- Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and DFT for Multi-die SoCs).
- Experience in fault modeling.
- Experience in SoC cycles, silicon bringup, and silicon debug activities.

About the Job:

In this role, you will define, design,



and analyze the DFT implementation and flow that supports the systems at the heart of the world's largest and most powerful computing infrastructure. The team develops from the lowest levels of circuit design to large system design and sees those systems all the way through to high-volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers, affecting millions of Google users.

The AI and Infrastructure team is redefining what's possible, empowering Google customers with breakthrough capabilities and insights by delivering AI and infrastructure at unparalleled scale, efficiency, reliability, and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

Responsibilities:

- Develop DFT strategy and architecture (e.g., hierarchical DFT, DFT for High speed I/Os, Analog DFT).
- Develop and drive die-level DFT validation strategy and complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.
- Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
- Document DFT architecture, test sequences, and boot-up sequences associated with test pins.
- Generate and deliver the production and debug patterns to the Post Silicon engineering team and run diagnosis for post-silicon supports.

Additional Information:

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📌 Senior DFT Design/Micro architect Engineer, Google Cloud (Bengaluru)
🏢 Google
📍 Bengaluru