Description

We are seeking a skilled ASIC RTL Engineer to join our team in India. The ideal candidate will have extensive experience in designing and developing RTL code for ASICs, contributing to various phases of the design process.

Responsibilities

- Design and develop RTL code for ASICs using Verilog/VHDL.
- Perform functional verification and ensure the design meets specifications.
- Collaborate with cross-functional teams including design, verification, and physical design.
- Support synthesis and timing closure activities for ASIC designs.
- Participate in design reviews and provide constructive feedback.
- Debug and resolve design issues throughout the development lifecycle.

Skills and Qualifications

- 7-9 years of experience in ASIC design and development.




- Proficiency in RTL design using Verilog or VHDL.
- Strong understanding of digital circuit design principles.
- Experience with synthesis tools and methodologies.
- Familiarity with simulation and verification tools such as ModelSim or Synopsys VCS.
- Knowledge of timing analysis and optimization techniques.
- Ability to work collaboratively in a team setting and communicate effectively.

Skills: fpga prototyping , Debugging Tools, Verilog, Synthesis, Rtl Design, Physical Design, low power design, systemverilog, Timing Closure

Experience: 7.00-9.00 Years

📌 ASIC RTL Engineer (Kochi)
🏢 Creeno Solutions Private
📍 Kochi