Job DescriptionLead Static Timing Analysis (STA) Engineer
NExperience: 6 to 10 years of experience in STA.
NLocation:- Bangalore
NJob Summary
nThe Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and physical design teams to achieve the target operating frequency and performance metrics.
NKey Responsibilities
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- Timing Sign-off and Analysis N
- Timing Closure Ownership: Drive all aspects of timing closure from pre-layout to post-layout for blocks, sub-systems, and/or the full chip. N
- Constraint Management: Develop, validate, and maintain Synopsys Design Constraints (SDC) and timing constraints for all functional and test modes (e.G., Scan, MBIST). N
- MMMC Analysis: Perform comprehensive timing analysis across multiple operating corners (Process, Voltage, Temperature - PVT) and various modes (Multi-Mode Multi-Corner).



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- Critical Path Identification: Analyze timing reports to identify and debug critical paths and resolve all Setup and Hold violations. N
- Signal Integrity (SI) &Noise;: Incorporate advanced timing effects such as on-chip variation (OCV), signal integrity (crosstalk), and voltage drop (IR-drop aware STA) into the sign-off process. N

nMethodology and Flow
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- Develop, maintain, and enhance STA flows and methodologies to improve efficiency, robustness, and reduce analysis runtime. N
- Automate repetitive tasks and report generation using scripting languages. N
- Generate final timing reports and sign-off collateral for tape-out. N

nEducation
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- Bachelor's or Master's degree in Electrical Engineering (EE), Electronics Engineering, VLSI, or a related field. N

nTechnical Skills
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- EDA Tools: Expert proficiency with industry-standard Electronic Design Au

📌 Lead Static Timing Analysis (Karnataka)
🏢 Leadsoc Technologies
📍 Karnataka