Job DescriptionLocation: Noida, Bangalore & Hyderabad
NExperience: 2-8 years
NAvailability: Immediate Joiners Only
NJob Description
nWe are seeking a solid Digital Physical Design Engineer to drive block-level physical implementation of complex SoCs/ASICs across advanced nodes.
NThe role involves hands-on execution and ownership of key blocks from synthesis to tape-out, ensuring closure across timing, power, area, and signoff quality, while collaborating with cross-functional teams and contributing to flow improvements.
NResponsibilities
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- N
- Execute physical designactivities including floor planning, power planning, placement, CTS, routing, and STA for assigned blocks N
- Drive timing closure across multi-mode, multi-corner scenarios N
- Perform physical verification (DRC, LVS, Antenna) and resolve violations to achieve clean signoff N
- Conduct power integrityanalysis (IR drop, EM) and support PDN optimization N
- Support DFT implementation and ensure proper test structure integration N
- Analyze and debug timing, congestion, power,



and signal integrity issues N
- Execute ECOs and support tape-out readiness under tight schedules N
- Develop and use automation scripts to improve flow efficiency N
- Contribute to methodology improvements and standardization efforts N
- Collaborate with team members on implementation strategies, constraints, and floorplans N

nQualification
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- N
- Bachelor's or Master's degree in Electronics / Electrical Engineering or related field N
- 2–6 years of hands-on experience in digital physical design of SoCs or ASICs N
- Proficiency with industry-standard EDA tools (Fusion Compiler / Innovus / ICC2, Tempus / PrimeTime, Voltus / RedHawk, Calibre) N
- Solid understanding of: N
- ○ Floorplanning and power planning basics N
- ○ Placement and routingoptimization N
- ○ Clock tree synthesis (CTS) N
- ○ Static Timing Analysis (STA) and timing closure techniques N
- ○ Physical verificationand reliability ch

📌 Senior Pd Engineer (Faridabad)
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